1. Field of the Invention
The present invention generally relates to a semiconductor memory; and particularly, to a non-volatile semiconductor memory (such as, flash memory or the like). The present invention relates to a non-volatile semiconductor memory, which has reduced fluctuation of writing speed when the data is written to memory cells.
2. Description of the Related Art
A flash memory generally includes a non-volatile memory cell having a control gate connected to the word lines, a drain connected to the bit lines, a source connected to the source lines and a floating gate, and includes a memory cell array composed of a plurality of the non-volatile memory cells arranged in the shape of a matrix.
In the flash memory, writing (programming) operation to each memory cell can be executed by applying a predetermined high voltage to each control gate and drain to make conductive a transistor of memory cell and then injecting channel hot electrons to the floating gate in order to accumulate electrons in the floating gate.
In view of attaining higher writing speed, a voltage applied to the drain of each memory cell must be set as high as possible during the writing operation. However, if the drain voltage is set to an excessively higher value, drain disturbance occurs in the non-selected memory cells adjacent to the selected memory cells; thereby, resulting in charge-loss in which the electrons accumulated in the floating gate are lost. Therefore, a level of the drain voltage must be within a predetermined constant range.
A flash memory includes a writing circuit which comprises a voltage boost circuit and a regulation circuit and controls the writing (programming) operation to the memory cells. The writing circuit is connected to each memory cell via the bit lines.
In the existing flash memory, the writing circuit generates a voltage VPUMP boosted from the power source voltage VCC in the voltage boost circuit and regulates the boosted voltage VPUMP to a predetermined constant level in the regulation circuit. Thereafter, during the writing operation, the writing circuit supplies the voltage Vbit regulated to the above constant level to the bit line connected to each memory cell as the drain voltage.
However, in recent years, a memory cell array is designed to have a wide area because a flash memory now has a larger capacity. Therefore, a longer bit line is also laid in the memory cell array. Accordingly, a voltage drop in the bit lines, which is generated by a writing current flowing into the memory cell during the writing operation, is also increased.
Therefore, it is difficult, in all memory cells within the memory cell array, to maintain the level of drain voltage to the predetermined constant range during the writing operation. When the level of the drain voltage is fluctuated in each memory cell during the write operation, it causes a problem such that fluctuation of the writing speed depending on the positions of the memory cells within the memory cell array is generated. This problem will prevent higher speed operation of a flash memory.
The present invention has been proposed with the above problems in mind; and it is therefore a general object of the present invention to provide high speed operation of a flash memory by reducing fluctuation of the writing speed in each memory cell of the memory cell array.
Another and a more specific object of the present invention is to provide a semiconductor memory comprising: a memory cell array including a plurality of memory cells which is disposed at intersections of a plurality of bit lines and word lines and are connected to said bit lines; and a writing circuit which receives an address signal and supplies a bit line voltage to the bit line connected to the memory cell selected with said address signal during writing operation, wherein said writing circuit changes, based on said address signal, a level of said bit line voltage depending on a position of said selected memory cell in said memory cell array.
At least a part of the writing address is inputted to the writing circuit during writing operation. The writing circuit of the present invention operates, based on the inputted writing address, to more increase a level of the bit line voltage supplied to the memory cell to which the wiring distance via the bit line from the output end of the bit line voltage of the writing circuit is longer. Therefore, the bit line voltage of the adequate level, depending on the position of the memory cell in the memory cell array, can be supplied to each memory cell; and thereby, fluctuation of writing speed in each memory cell of a memory cell array is reduced.